Espressif Systems /ESP32-S2 /I2C0 /CTR

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Interpret as CTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SDA_FORCE_OUT)SDA_FORCE_OUT 0 (SCL_FORCE_OUT)SCL_FORCE_OUT 0 (SAMPLE_SCL_LEVEL)SAMPLE_SCL_LEVEL 0 (RX_FULL_ACK_LEVEL)RX_FULL_ACK_LEVEL 0 (MS_MODE)MS_MODE 0 (TRANS_START)TRANS_START 0 (TX_LSB_FIRST)TX_LSB_FIRST 0 (RX_LSB_FIRST)RX_LSB_FIRST 0 (CLK_EN)CLK_EN 0 (ARBITRATION_EN)ARBITRATION_EN 0 (FSM_RST)FSM_RST 0 (REF_ALWAYS_ON)REF_ALWAYS_ON

Description

Transmission setting

Fields

SDA_FORCE_OUT

0: direct output. 1: open drain output.

SCL_FORCE_OUT

0: direct output. 1: open drain output.

SAMPLE_SCL_LEVEL

This register is used to select the sample mode.

1: sample SDA data on the SCL low level.

0: sample SDA data on the SCL high level.

RX_FULL_ACK_LEVEL

This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.

MS_MODE

Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave.

TRANS_START

Set this bit to start sending the data in TX FIFO.

TX_LSB_FIRST

This bit is used to control the sending mode for data needing to be sent.

1: send data from the least significant bit.

0: send data from the most significant bit.

RX_LSB_FIRST

This bit is used to control the storage mode for received data.

1: receive data from the least significant bit.

0: receive data from the most significant bit.

CLK_EN

Reserved.

ARBITRATION_EN

This is the enable bit for I2C bus arbitration function.

FSM_RST

This register is used to reset the SCL_FSM.

REF_ALWAYS_ON

This register is used to control the REF_TICK.

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